Compact modeling refers to the creation of integrated semiconductor models used for simulating circuits. Designers of integrated circuits (ICs) constantly seek models that accurately replicate the behavior of the device being tested, while also being simple enough for circuit simulations. Many semiconductor technology engineers consider physics-based compact models to be the most precise, as they can cover a wide range of operating conditions.
However, these models are specifically based on the physics of the device technology and are focused solely on the individual transistor rather than the overall circuit. The inherent nature of these models and the complexity of the equations involved makes them less computationally efficient for circuit-level simulators. Consequently, the development of the accurate and time-efficient equation-based compact models remains of great interest to foundries and Fabless design centers. This interest arises due to the increasing operating frequencies of circuits and the demanding tolerances requested by customers.
Compact Model Extraction
Compact transistor models are built using quasi-isothermal pulsed IV, Pulsed S-parameters measurement data, and Load Pull characterization for model validation. These models consider complex phenomena such as electro-thermal and trapping effects to enable simulation under modulated signal conditions.
Compact modeling stands as the most critical step in the circuit design process. It serves as the cornerstone for achieving a successful initial design, reducing time to market, and facilitating information exchange between the transistor manufacturer and circuit designers.
Pre-RF Pulsed IV Measurements for Enhanced Transistor Compact Modeling
MT930C2 is an add-on software module for MT930C Vector-Receiver Load Pull and MT930J Pulsed IV Curves which measures the I-V characteristic of GaN HEMT transistors in pulse mode by considering the “real” state of charge of the traps, i.e., the one imposed by the component’s environment in its final application. The measurement involves applying a RF pre-pulse before each IV measurement point which conditions the charge of the traps at a level determined by the I-V area and is varied throughout the measurement to represent the signal envelope’s evolution. The solution uses vector-receiver load pull measurements to set the impedance states to match the final application and set the load lines appropriately.
MT930C2 has been developed to create a more accurate compact transistor model and to speed-up the model extraction and validation process. MT930C2 simplifies the trap models development and embeds non-50ohm measurements into the model extraction process.