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A Sub 1Ω Load-Pull Quarter-Wave Prematching Network Based on a Two-Tier TRL Calibration

AUTHORS: John F. Sevic – Spectrian Corporation, Sunnyvale, California

PUBLICATION HISTORY: First published in the Microwave Journal, March 1999, Vol. 43, No. 3 and republished with permission in this format in December 2002.

ABSTRACT: Transistors used for cellular and PCS infrastructure applications are required to amplify signals with a peak-to-average ratio that can exceed 13 dB, resulting in a peak envelope power (PEP) approaching 1 kW. This PEP requirement is a consequence of simultaneous amplification of multiple digitally modulated carriers with a time-varying envelope and requires a load resistance in the neighborhood of 0.3Ω. Present load-pull technology based on mechanical tuners is limited to approximately 1Ω at cellular and PCS frequencies, which renders these systems incapable of characterizing transistors under these conditions. Quarter-wave prematching networks nave been developed to transform the source- and load-pull domains to a lower impedance. A variety of techniques have been used to characterize these quarter-wave networks, including standard vector network analyzer (VNA) error correction. This article presents a further refinement of this characterization technique, which is based on a two-tier calibration using 7mm and microstrip thru-reflect-line (TRL) calibrations.